1. Field of Invention
The present invention is related to a method of controlling operations of a dynamic random access memory (DRAM), and more specifically, to a method of controlling operations of a delay locked loop (DLL) of the DRAM.
2. Description of Related Art
Typically, an electronic system includes a number of integrated circuit chips that communicate with one another to perform system applications. Often, the electronic system includes a controller, such as a micro-processor, and one or more memory chips, such as random access memory (RAM) chips. The controller communicates with the memory to store data and to read the stored data.
Sometimes, data and strobe signals are communicated between chips, such as a controller and RAM, to read and write data. To write data from the controller to the RAM, data and a clock or strobe signal are transmitted to the RAM and the received data is clocked into the RAM via the clock signal. To read data from the RAM, output data and a strobe signal are transmitted from the RAM. The output data and strobe signal are aligned to a clock signal via a delay locked loop (DLL).
Typically, the RAM receives an external clock signal and the DLL receives the external clock signal or an on-chip clock signal based on the external clock signal. The DLL provides an internal clock signal based on the external clock signal. The internal clock signal clocks the output data and strobe signal out of the RAM via output circuitry. The internal clock signal is fed back to a phase detector via a delay that mimics the delay of the output circuitry. The DLL aligns and locks the delayed internal clock signal to the external clock signal, which aligns the output data and strobe signal to the external clock signal. Since the external clock signal may drift over time and changes in the supply voltage and temperature may cause timing changes, the DLL runs continuously to maintain a lock state, which consumes considerable current.
In standby mode, integrated circuit chips are put into a low power state. If a DLL runs continuously in standby mode, the DLL is ready to drive output data as soon as the chip comes out of standby mode, however, considerable power is consumed in standby mode. If the DLL is switched off or loses lock state in standby mode, it takes considerable time to exit standby mode because the DLL must re-acquire lock state. As speeds increase and power consumption becomes more critical, these problems are amplified.
FIG. 1 is a conventional DLL 100 of a dynamic random access memory (DRAM). Referring to FIG. 1, the DLL 100 has a phase detector 110, a delay line circuit 120, and an output buffer 130. The phase detector 110 receives an external clock signal XCLK and compares the external clock signal XCLK with a feedback clock signal CLK received from the output buffer 130. The phase detector 110 adjusts a delay of the delay line circuit 120 according to the comparison result of the external clock signal XCLK and the feedback clock signal CLK to synchronize the external clock signal XCLK with the feedback clock signal CLK. The output buffer 130 outputs the feedback clock signal CLK as an internal clock signal. The delay line circuit 120 and the output buffer 130 are active only when the voltage level of an enable signal IDDL is high.
FIG. 2 is a timing diagram of signals of the DLL 100 shown in FIG. 1. Referring to FIGS. 1 and 2, when a voltage level of a clock enable signal CKE is low, the DRAM is in a standby mode (e.g. a pre-charge power down (IDD2P) mode) to reduce the power consumption of the DRAM within a standby period Ta. Every a predetermined update interval Tb within the standby period Ta, the enable signal IDDL is pulled from a low level to a high level, such that the delay line circuit 120 and the output buffer 130 are active within the enable periods Tc periodically to maintain the lock state of the DLL 100. However, the lengths of the predetermined update interval Tb and the enable periods Tc are fixed and determined based on the periods of the external clock signal XCLK. Therefore, an extra clock counter is required to count a number of clocks of the external clock signal XCLK to determine the beginnings and the ends of the enable periods Tc accordingly. However, the clock counter increases the consumed power of the DRAM even when the DRAM is in the standby mode, and the DRAM, thus, may not operate correctly to conform to the specification of the standby mode.